The present disclosure relates generally to methods and systems for addressing memory with variable density, and—in particular—to flexible and efficient addressing schemes for non-volatile memory with variable memory density, in other words, memory with selectable memory capacity. In the following, for illustration purposes, the invention will be described with reference to addressing schemes for NOR-flash memory. However, the disclosure is not so limited and may find its application in conjunction with addressing memory with variable density based on other memory technologies.
Advanced concepts for a NOR-flash memory architecture assume that—besides the conventional way of storing information in the form of one bit per memory cell/flash cell (storage location)—also multiple bits, for example three bits, may be stored in two memory cells. However, in some applications, both concepts with a first memory density of one bit per memory cell and a second memory density of p bits stored in q memory cells with p>q should be implemented in the same hardware such as the same integrated circuit device. In other words, the extension of the memory capacity based on choosing the second memory density or second memory capacity in the same memory device should be selectable during operation.
This selectability in the same memory device results in problems with implementing simple addressing schemes for both, a first operation mode of the memory device with the first memory density or first memory capacity and at least one second operation mode of the memory device with at least the second memory density or second memory capacity.
Hence, systems and methods for simplifying an addressing scheme for a memory device with selectable or variable memory density would be desirable.